DVD27 harman/kardon
ST72F324L, ST72324BL
1 INTRODUCTIONtion set and are available with FLASH or ROM pro-
gram memory.
The ST72F324L and ST72324BL devices are
Under software control, all devices can be placed
members of the ST7 microcontroller family de-
in WAIT, SLOW, ACTIVE-HALT or HALT mode,
signed for the 3V operating range. They can be
reducing power consumption when the application
grouped as follows:
is in idle or stand-by state.
- The 32-pin devices are designed for mid-range
The enhanced instruction set and addressing
applications
modes of the ST7 offer both power and flexibility to
- The 44-pin devices target the same range of ap-software developers, enabling the design of highly
plications requiring more than 24 I/O ports.efficient and compact application code. In addition
All devices are based on a common industry-to standard 8-bit data management, all ST7 micro-
standard 8-bit core, featuring an enhanced instruc-controllers feature true bit manipulation, 8x8 un-
signed multiplication and indirect addressing
modes.
Figure 1. Device Block Diagram
8-BIT COREPROGRAM
ALUMEMORY
(8K - 60K Bytes)
RESET
CONTROL
VPP
RAM
(384 - 2048 Bytes)
VSS
VDD
WATCHDOG
OSC1
OSC
OSC2
ADDRESS AND DATA BUS
MCC/RTC/BEEP
PA7:3
PORT A
(5 bits on J devices)
PORT F(4 bits on K devices)
PF7:6,4,2:0
(6 bits on J devices)
(5 bits on K devices)TIMER A
PB4:0
PORT B
(5 bits on J devices)
BEEP
(3 bits on K devices)
PORT E
PE1:0
PORT C
(2 bits)
SCI
PC7:0
TIMER B
(8 bits)
PORT D
PD5:0SPI
(6 bits on J devices)
(2 bits on K devices)10-BIT ADC
VAREF
VSSA
3
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ACEC
